1. 1x Slot
2. Pcie 1x Slot

In a previous blog post, we covered the difference between PCI and PCI-X. The response to the post was enthusiastic, and we were asked to write a complementary post explaining the difference between PCIe x1, x4, x8, x16. We are always happy to answer customers’ questions (feel free to contact us with your questions regarding industrial computers).

The short answer is:

PCI Express supports 1x 2.5Gbps, 2x, 4x, 8x, 12x, 16x, and 32x bus widths transmit / receive pairs. The differential pins Lanes listed in the pin out table above are LVDS which stands for: Low Voltage Differential Signaling. PCI-Express 1x Connector Pin-Out.

PCI Express devices communicate via a logical connection called an interconnect or link.A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests (configuration, I/O or memory read/write) and interrupts (INTx, MSI or MSI-X). GLOTRENDS 1X to 1X PCI-E Extension Cable 0.6M for Hidden Pcie Slot, Limited Space Installation,Saving Your Blocked PCIe Slot,Come with USB3.0 Cable (UEX101) 4.3 out of 5 stars 288 $11.82 $ 11. We would like to show you a description here but the site won’t allow us.

• ‘PCIe x1’ connections have one data lane
• ‘PCIe x4’ connections have four data lanes
• ‘PCIe x8’ connections have eight data lanes
• ‘PCIe x16’ connections have sixteen data lanes

The long answer:

The more data lanes in a connection, the more bandwidth between the card and the host. However, there is usually a cost increase incurred with higher lane counts.

PCIe is an updated version of the PCI protocol. Similar to PCI/PCI-X interfaces, PCIe was developed for peripheral component interconnection. PCIe differs from PCI/PCI-X in several ways, but this blog won’t cover most of those differences. However, one key difference will allow us to better understand the differences between the variations of the PCIe protocol (x1, x4, x8, x16 and x32). That key difference is ‘parallel’ versus ‘serial’ data transmission.

1x Slot

In PCI and PCI-X architecture, all of the cards share parallel data lines to and from the host. Differences between card-speeds and slot-types regularly result in throttled data speeds.

In the PCIe architecture, Each card has it’s own dedicated serial data connections (lanes) to the host. This allows each card connection to achieve a bandwidth independent of other cards that may be active in the system. The number of lanes are indicated by the suffix of the PCIe protocol (×1, ×4, ×8, ×16, ×32). Each lane is capable of speeds from 250-1969 MB/s, depending on the version of the PCIe protocol (v1.x, v2.x, v3.0, v4.0).

PCIe cards can always operate in PCIe slots with the same or more lanes than the card. For example, an x8 card can operate in a slot with x8, x16, or x32 lanes. Similarly, an x1 card can operate in any PCIe slot.

caveat:

Sometimes, a PCIe slot operates with fewer data lanes than the mechanical slot-type indicates. For example, sometimes a motherboard manufacturer will use an x16 mechanical slot even though the data connection is only x8. In these cases, the higher-bandwidth card still may work (for example, an x16 card in an x16 slot with only x8 connection), if the card doesn’t require that extra bandwidth. The following image shows the PCI connections of the motherboard used in DuroPC’s RAC355. Notice ‘SLOT 1/5’ are PCIe x16 slots but only have an x8 connection. Similarly, notice how ‘SLOT 7’ uses an x8 slot but only has an x4 connection. (Click the image to see a larger version.)

PCI Express as a high-bandwidth, low pin count, serial, interconnect technology. It was designed to replace the older PCI and AGPbus standards. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-swap functionality. PCI Express architecture provides a high performance I/O infrastructure for Desktop Platforms with transfer rates starting at 2.5 Giga transfers per second over a x1 PCI Express lane for Gigabit Ethernet, TV Tuners, Firewire 1394a/b controllers, and general purpose I/O. PCI Express architecture provides a high performance graphics infrastructure for Desktop Platforms doubling the capability of existing AGP8x designs with transfer rates of 4.0 Gigabytes per second over a x16 PCI Express lane for graphics controllers. A lane is composed of two differential signaling pairs, with one pair for receiving data and the other for transmitting.

ExpressCard utilizing PCI Express interface, developed by the PCMCIA group for mobile computers. PCI Express Advanced Power Management features help to extend platform battery life and to enable users to work anywhere, without an AC power source. The PCI Express electrical interface is also used in some computer storage interfaces SATA Express and M.2.

The broad adoption of PCI Express in the mobile, enterprise and communication segments enables convergence through the re-use of a common interconnect technology.

PCI-E is a serial bus which uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction [one transmit, and one receive pair]. PCI Express supports 1x [2.5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs].

The differential pins [Lanes] listed in the pin out table above are LVDS which stands for: Low Voltage Differential Signaling.

PCI-Express 1x Connector Pin-Out

PCI-Express 4x Connector Pin-Out

PCI-Express 8x Connector Pin-Out

PCI-Express 16x Connector Pin-Out

PRSNT#1 is connected to GND on motherboard.
Add on card needs to have PRSNT#1 connected to one of PRSNT#2 depending what type of connector is in use.

PCI-express standards

PCI Express 1.0a

In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250 MB/s and a transfer rate of 2.5 gigatransfers per second (GT/s). Transfer rate is expressed in transfers per second instead of bits per second because the number of transfers includes the overhead bits, which do not provide additional throughput; PCIe 1.x uses an 8b/10b encoding scheme, resulting in a 20% (= 2/10) overhead on the raw channel bandwidth.

PCI Express 2.0

PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s. Consequently, a 32-lane PCIe connector (×32) can support an aggregate throughput of up to 16 GB/s. PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 will work with the other being v1.1 or v1.0a. Like 1.x, PCIe 2.0 uses an 8b/10b encoding scheme, therefore delivering, per-lane, an effective 4 Gbit/s max transfer rate from its 5 GT/s raw data rate.

PCI Express 2.1

PCI Express 2.1 (dated March 4, 2009) supports a large proportion of the management, support, and troubleshooting systems planned for full implementation in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. The increase in power from the slot breaks backward compatibility between PCI Express 2.1 cards and some older motherboards with 1.0/1.0a, but most motherboards with PCI Express 1.1 connectors are provided with a BIOS update by their manufacturers through utilities to support backward compatibility of cards with PCIe 2.1.

PCI Express 3.0

PCI Express 3.0 specification was made available in November 2010. New features for the PCI Express 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. PCI Express 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the bandwidth overhead from 20% of PCI Express 2.0 to approximately 1.54% (= 2/130). This is achieved by XORing a known binary polynomial as a scrambler to the data stream in a feedback topology. PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0.

PCI Express 4.0

Pcie 1x Slot

PCI Express 4.0 was officially announced on 2017, providing a 16 GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0, while maintaining backward and forward compatibility in both software support and used mechanical interface. PCI Express 4.0 specs will also bring OCuLink-2, an alternative to Thunderbolt connector. OCuLink version 2 will have up to 16 GT/s (8 GB/s total for ×4 lanes), while the maximum bandwidth of a Thunderbolt 3 connector is 5 GB/s. Additionally, active and idle power optimizations are to be investigated.